1. Field of the Invention
The present invention generally relates to an overlay mark and a method of manufacturing the same, in particular, to an overlay mark and a method of manufacturing the same which may avoid influencing a measurement result of alignment accuracy and prevent occurrence of defects.
2. Description of Related Art
Currently, under the circumstance that integration of a semiconductor process is gradually enhanced, steps of the process become more and more complicated and troublesome. Therefore, it has become the developing direction of each semiconductor process manufacturer that how to use a real-time measurement apparatus in a process to monitor the process and promptly report defects, so as to reduce the loss caused by process errors.
As the line width of an integrated circuit (IC) process is continuously reduced, key success factors of a lithography process of a wafer include not only the control of critical dimensions (CD), but also alignment accuracy, which is quite important. Therefore, the measurement of the alignment accuracy is a critical step in the semiconductor process. An overlay mark is a mark for measuring an overlay error, and used to determine whether a photoresist pattern formed in the lithography process is aligned accurately with a pattern of a former layer.
Generally speaking, in a common non-volatile memory process, the following problems usually occur when measuring the alignment accuracy.
The non-volatile memory process includes forming isolation structures on a substrate; then, sequentially forming a dielectric layer serving as a material of a tunneling dielectric layer and a conductive layer serving as a material of a floating gate on the substrate; next, performing a planarization process to remove a portion of the conductive layer till the isolation structures are exposed; afterwards, forming a second dielectric layer on the substrate to serve as a material of an inter-gate dielectric layer; and finally, forming a photoresist pattern on the second dielectric layer, so as to perform a subsequent patterning process to define the inter-gate dielectric layer.
After the photoresist pattern is formed, the alignment accuracy is measured, so as to prevent generating an unexpected overlay error between the patterned second dielectric layer and a pattern of a former layer. The method of measuring an overlay error includes forming a photoresist pattern on the second dielectric layer on the isolation structures in the peripheral area while forming the photoresist pattern for defining the inter-gate dielectric layer, and then comparing the photoresist pattern in the peripheral area with the patterns of other isolation structures.
However, when the isolation structures are formed by using a chemical mechanical polishing (CMP) method, a dishing phenomenon often appears on the isolation structures due to low active area pattern density of the substrate, further resulting in that the conductive layer is remained on the isolation structures in the planarization process. Therefore, when measuring the alignment accuracy, the remained conductive layer will cause errors in a measurement signal, thereby influencing a measurement result or causing the problem that the overlay error value cannot be measured.
Furthermore, another method of measuring an overlay error includes forming the photoresist pattern serving as an overlay mark on the second dielectric layer in the active area in the peripheral area, and then measuring the alignment accuracy. Although this method will not influence the measurement of the alignment accuracy due to the dishing phenomenon of the isolation structures, an undercut phenomenon usually appears in a subsequent step of removing a conductive layer by a wet-etching process, resulting in removing the conductive layer under the photoresist pattern and causing the overlay mark to break down. As a result, defects are caused in the active area.